Communication devices include components having different voltage requirements that interface with each other. For example, a radio can have several components (e.g., a memory, a transceiver) on an inter-integrated circuit (I2C) serial bus and other components (e.g., a smart battery) on a system management bus (SMBUS). In theory, according to the technical specifications of these two buses, the buses should be able to interface directly with each other. In practice, however, this may not always be the case. The two buses (and thus the components thereon) often have different input and output voltages. An intermediate interface between the two buses is needed in order for the two sets of components to communicate with each other.
FIG. 1 illustrates a typical bi-directional buffer 100, which buffers data lines with a buffer integrated circuit (IC), such as, for example, 74VCX163245GX or an equivalent. A typical bi-directional buffer includes data ports 120 and 190, respectively, supplying Data A and Data B, bonding pads 130, 140, 180, uni-directional tri-stateable drivers 160, 170, and inverter 150. Buffer ICs of this type can control the data direction with an additional input pin T/R 110. The signal at input pin T/R 110 indicates to the circuit whether data is going from port 120 to port 190 or port 190 to port 120. Such a buffer IC is typically considered a good interface between a microprocessor bus and a memory bus.
Without a directional control signal, a drawback of using buffer ICs arises when either of the connected components can begin a data transfer based only on the presence or absence of activity on the data line. Without a directional control signal from the components, the direction of the data flow cannot be determined beforehand. This occurs when, for example, the drivers of the serial data lines are an inter-integrated circuit (I2C) or a system management bus (SMBUS) devices. With these devices, there is no external control signal available to indicate the data direction for the bi-directional buffer 100. With no directional control signal, since data can travel both ways, it is possible for contention to occur along the data path, i.e., data from each direction conflicting on ports 120 or 190.
Another device considered for buffering input/output signals is a pass transistor. The pass transistor is configured to always be on and provide open collector buffering of two signals. FIG. 2 illustrates an example of a pass transistor circuit 200 implemented between two typical integrated circuit input/output ports, which provides the ability to interface signals with different voltage levels defined for logic 1 state, such as 3.3 v and 2.5 v. More particularly, the circuit 200 includes IC data IN 215, 255, IC data OUT 225, 245, IC tri-state control 210, 250, IC tri-state output buffers 220, 240 (an output from the component), bonding pads 224, 244, IC input buffers 222, 242 (an input to the component), pass transistor 230, and two pull-up resistors 231, 232. In the figure, the pass transistor 230 is disposed between a pair of integrated circuit (IC) input/output (I/O) pads having input buffers and tri-state output buffers connected back to front. The direction that the signal passes through the pass transistor 230 is determined by the tri-state control signals 210, 250. Each tri-state control signal 210, 250 forces its associated tri-state buffer to a high impedance state or to the operational state. The value of the pull-up resistors is determined by the voltage level and drive current requirements of the IC pins being buffered.
When the logic 1 voltage levels or output drive current requirements of the buffered signals are significantly different, one of the buffered devices becomes unable to achieve a voltage level low enough to be recognized as logic 0. Typically, for current CMOS devices, the highest voltage level guaranteed to be recognized as logic 0 is 30% of the full logic 1 level, or 0.99 v for 3.3 v logic or 0.75 v for 2.5 v logic. This reduces the noise margin for the logic 0. With the pass transistor always being on, the pull-up resistors required to pull the signal on each side of the pass transistor to logic 1 appear in parallel to the two output drivers. The effective apparent parallel combination of the two separate pull-up resistors causes the device with the output with the lower sink current capability to be unable to drive its output voltage level low enough to be recognized as logic 0. Increasing the value of the pull-up resistors increases the overall resistance, which assists the device in achieving a logic 0 output with the weaker output. However, the larger resistances cause the output of the second device to have an excessive rise time when it releases the signal to logic 1. Additionally, with independent tri-state control signals, both devices may attempt to drive the interface at the same time.
Currently, a significant amount of circuitry and processor memory space is used to interface these different components. Consequently, a method or interface for bi-directional buffering, which provides direction control without a separate control signal and the ability to buffer different input/output voltages from interfaced components across a signal bus, is desirable.